The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed. 4-bit ripple type counters partitioned into two sections. Each counter has a di- vide-by-two. The 74LS90 is a simple counter, i.e. it can count from 0 to 9 cyclically in its natural mode. It counts the input pulses and the output is received as a 4-bit binary. 74LS90N Datasheet, 74LS90N PDF, 74LS90N Data sheet, 74LS90N manual, 74LS90N pdf, 74LS90N, datenblatt, Electronics 74LS90N, alldatasheet, free.
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Search the history of over billion web pages on the Internet. Full text of ” IC Datasheet: Each section can be used separately or tied together Q to CP to form BCD, bi-quinary, modulo, or modulo-1 6 counters.
74LS90N Datasheet catalog
The Output LOW drive factor is 2. The Qg Outputs are guaranteed to drive the full fan-out plus the CPi input of the device. To insure proper operation datasyeet rise tr and fall time tf of the clock must be less than 1 00 ns.
State changes of the Q outputs do not occur simultaneously because of datasheey ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Qq output of each device is designed and specified to drive the rated fan-out plus the CP- input of the device.
Since the output from the divide-by-two section is datahseet internally connected to the succeeding stages, the devices may be operated in various counting modes. The input count is then applied to the CPi input and a divide-by- ten square wave is obtained at output Qq. The first flip-flop is used as a binary element for the divide-by-two function CPq as the input and Qq as the output.
74LS90 BCD Counter IC Pin Diagram, Configuration, Equivalent & Datasheet
The CP- input is used to obtain binary divide-by-five operation at the Q3 output. The CPq in- put receives the incoming count and Q3 produces a sym- metrical divide-by-twelve square wave output.
The first flip-flop is used as a binary element for the divide-by-two function. The CPi in- put is used to obtain divide-by-three operation at the Q- and Q2 outputs and divide-by-six operation at the Q3 out- put.
The input count pulses are applied to input CPq.
Simultaneous divisions of 2, 4, 8, and 1 6 are performed at the Qq, QiDataxheet. Simultaneous frequency divisions of 2, 4, and 8 are available at the QiQ2, and Q3 outputs.
Independent use of the first flip-flop is available if the datashdet function coin- cides with reset of the 3-bit ripple-through counter. Output Qq is connected to Input CPi. Not more than one output should be shorted at a time, nor for more than 1 second.